1. Field of the Invention
The invention relates to the process for providing nitrogen in a semiconductor substrate, particularly for forming an oxide region using differential oxide growth.
2. Description of the Related Art
A prevalent trend in the semiconductor industry is to increase the density of semiconductor devices formed on silicon substrates.
Programmable logic devices (PLD) are circuits which can be configured by a user to perform logic functions or serve as memory arrays. Generally, PLDs include a programmable array of cells and array control circuitry which is utilized to program the array with the desired implementation. The programmable array comprises a series of low-voltage, short channel floating gate transistors which store charge to reflect whether a particular cell is programmed with a bit of data. The programmed array reflects in a particular user's individual configuration for the programmable device, allowing users to customize the programmable logic device for a number of different applications.
One type of programmable logic device which has become popular due to its performance and cost characteristics are electrically erasable (E.sup.2) CMOS programmable devices.
Erasable CMOS technology is based on the concept of a stored charge on a floating gate. Electrons are transferred to the gate through a physical mechanism known as Fowler-Nordheim tunneling. For an electrically erasable cell, a tunnel oxide is present between the source and drain regions and the floating gate that is about one-third of the thickness of a traditional transistor gate oxide. Fowler-Nordheim tunneling involves placing a potential across the tunnel oxide which distorts the electric field and allows electrons to traverse the tunnel oxide upon which they become trapped on a floating gate.
The control circuitry of the cell--the program transistors--essentially comprise high voltage transistors capable of sustaining high electric fields. So called read transistors, which operate at low voltage, include a first junction, second junction and gate (defined by the word line of the device). The gate is comprised of a program junction separated from a floating gate by an oxide layer having a thickness of approximately 180 .ANG.. The program transistor includes a first junction, second junction and a gate which also rests on the oxide layer. The memory cell will also include a floating gate, separated from the program junction by a tunnel oxide which may be activated by the control gate. The thickness of tunnel oxide is in a range of approximately 80-100 .ANG..
The trend of E.sup.2 PLD devices has been toward lower and lower supply voltages. Consequently, this has required a corresponding scaling down of transistor size, both in terms of channel length and junction depths, and the gate oxide, including two different oxide thicknesses for the gate and tunnel oxides.
In reducing the size of semiconductor devices much of the focus has been on reducing the length L of the gate. As the gate length L is reduced, however, the device size must also be reduced in the vertical direction--that is, the source-drain junction depths (x.sub.j) and oxide thicknesses must be reduced.
There are generally two ways to make a doped region shallower. One way is to implant ions at a lower energy (e.g., 1 keV instead of 20 keV). The second way to reduce the amount of dopant diffusion is to reduce anneal time and/or temperature. Annealing and other heat steps cause the doped regions to diffuse, thus causing the doped regions to expand and deepen in thickness. The longer the time and the higher the temperature of a heat step, the deeper the doped regions become.
In common processes, both deep source-drain and source-drain extension regions are annealed simultaneously, or source-drain extension regions are annealed and then re-exposed to anneal temperatures during the deep source-drain region anneal. These anneal steps cause both types of regions to deepen as a result of diffusion. By annealing for a shorter time or at a lower temperature, the source-drain extension region thickness can be minimized, especially if a low energy implant of the source-drain extension region is also used. Nonetheless, a reduced anneal would also cause the deep source-drain regions to be formed too shallow. Too shallow an deep source-drain region is undesirable because it alters device characteristics (e.g., device resistivity and drive current) and makes formation of reliable contacts difficult. Silicidation of deep source-drain regions eats into the deep source-drain depth, causing an already shallow deep source-drain region to be even further reduced.
Thus, even using a low energy source-drain extension implant with conventional device formation processes, the manufacturer has very limited control over maintaining shallow source-drain extension thickness because of diffusion resulting from subsequent anneal and other heat steps and because deep source-drain depth must be maintained.
As the gate oxide thicknesses have been scaled down, they have reached and become even thinner than the tunnel oxide on lightly or undoped silicon. Traditionally, the manufacturing process for implementing all four types of cells requires a large number of sequential process steps. The reduction in processing steps, and specifically masking steps, is an objective of nearly every process engineer. Each savings of a masking step may result in a significant saving in the cost of manufacture of the particular device.